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# Design Rule Verification Report

Date | : | 13/12/2014
Time | : | 20:54:20
Elapsed Time | : | 00:00:00
Filename | : | C:\Users\ÓscarRamón\Desktop\TELECOMUNICACIONES\CUARTO\1º Cuatrimestre\Tecnologia de Circuitos Impresos\integrated project\proyecto altium\PROYECTO\PCB\circuito_v3.PcbDoc

Warnings | : | 0
Rule Violations | : | 0

## Summary

Warnings | Count
--- | ---
Total | 0

Rule Violations | Count
--- | ---
Short-Circuit Constraint (Allowed=No) (All),(All) | 0
Un-Routed Net Constraint ( (All) ) | 0
Clearance Constraint (Gap=10mil) (All),(All) | 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) | 0
Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All) | 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) | 0
Total | 0